Hi shtaxxx-san,
I noticed Pyverilog fail to analyze verilog code as follows (case statement is written in function).

  function func1;
    input in1;
    input sel;
    case(sel)
        'h0:
          func1 = in1;
        default:
          func1 = 1'b0;
    endcase
  endfunction

So first, I modified Bindvisitor._case change to same implementation with Signalvisitor._case.
But by only this change, case statement is not analyzed correctly.

I found that Bindvisitor.getCondlist and Bindvisitor.getFlowlist doesn't work correctly for functioncall and match_flowlist became blank. So in the following lines, tree is added in the unexpected form.

'tree = reorder.reorder(
self.appendBranchTree(current_tree, match_flowlist, add_tree))'

So I commented out 'if frame.isFunctioncall(): break' in Bindvisitor.getCondlist and Bindvisitor.getFlowlist.

Under this modification, match_flowlist is valid (not blank), and added tree in correct form.

But in honest, I don't understand why this line was inserted, and it can be deleted.
Please give me advise if there are other good correction method.

With this modification, analysis result of testcode/function.v was changed. (I think previous analysis result is not correct.)